1. Field of the Invention
The invention relates to a method for the production of MOS transistors with extremely low leakage currents at the pn junctions, and also of logic/switching transistors, whose gates are laterally limited with spacers in a p-substrate or a p-well in an n-substrate.
2. Discussion of the Related Art
In standard DSM-MOS transistors (DSM: Deep Submicron Silicon Technology), the poly/silicide/salicide gates are provided with spacers to limit the leakage currents. In this manner, different materials are superimposed in the regions between the spacers. As a general rule, though, these materials are not exclusively silicon, polysilicon, silicon oxides and silicon nitrides. These materials naturally have different material properties, such as different coefficients of expansion. In connection with the deposition temperatures and the temperature loads that in particular the spacers experience during the overall production process, a mechanical stress arises at the spacer edges, among other places, finally resulting in increased leakage currents. These increased leakage currents are also initiated or increased via the implantation of high As doses (e.g., >E15/cm2).
Furthermore, lattice defects cannot be completely annealed out because of the limited thermal budget of the production process, so that leakage currents can likewise be generated. The pn leakage currents are entirely acceptable for digital CMOS applications, but not for analog dynamic memories (e.g., image sensors). These leakage currents would substantially degrade the image information in the image sensors.
One known way to reduce these leakage currents is to perform an additional deep p diffusion, while retaining the spacers and the high-dose As implantation. This does not eliminate the causes of the leakage current, but reduces the effects of the leakage current. The defects are now within n regions, where most of them are inactive. However, a statistical number of these defects “grows” out of the additional p diffusion regions, and is hence active again. It is hardly possible to prevent that, so that significant and difficult to quantify yield risks remain and arise.
However, since diffusion is not just vertical, but also lateral, this leads to greater channel length, lower packing densities, increased parasitic elements (e.g., capacitances, propagation times), lower performance and, finally, higher costs.